Reference is made to a copending application filed on the same date as this application listing as inventors Zhiqiang Wu, Li Li, Thomas Figura, Kunal Parekh, Pai Pan, Alan Reinberg, and Manny Ma, and entitled "Ion Implanted Structures And Methods of Formation".
During fabrication of integrated circuitry, it is often desirable to form contact openings over a substrate. Often times, many layers of material overlie the substrate so that forming a desired contact opening necessarily involves etching through different overlying layers of material.
As an example, and referring to FIGS. 1-3, a semiconductor wafer fragment is shown generally at 10. Fragment 10 includes a top surface 12 atop which two laterally spaced apart conductive lines 14 are formed. Lines 14 comprise respective polysilicon layers 16, silicide layers 18, and insulative nitride caps 20, all of which having been formed by a previous anisotropic etch. Lines 14 also include insulative sidewall spacers 22. A thin oxide layer 24 is formed over the substrate and conductive lines 14, and typically comprises an oxide formed from decomposition of tetraethyloxysilane (TEOS). A layer 26 of borophosphosilicate glass (BPSG) is formed over layer 24 as shown.
Referring to FIG. 2, one prior art problem associated with forming a contact opening to wafer or substrate 10 is illustrated. Typically, a contact opening 28 is anisotropically etched between conductive lines 14 to a degree sufficient to expose an area 30 of the substrate between the conductive lines and to which electrical connection is to be made. Typical etch chemistries for etching contact opening 28 etch BPSG layer 26 at a much faster rate than TEOS layer 24. Accordingly, when the anisotropic etch reaches TEOS layer 24 between contact lines 14 (FIG. 1), such must be conducted for a longer period of time to ensure that TEOS layer 24 is completely removed to adequately expose area 30. Such etch, due in part to the differing etch rates between TEOS layer 24 and BPSG layer 26, can overetch the inner-most side wall spacers 22 and erode nitride cap 20 thereby undesirably exposing silicide 18 as shown for the right-most conductive line 14 in FIG. 2. Such condition can and does cause shorting between adjacent lines or devices thereby rendering such devices useless.
Referring to FIG. 3, a prior art solution to the above-described problem is shown in which contact opening 28 is made to be narrower between conductive lines 14. As shown, the sides of contact opening 28 coincide with inner-most side wall spacers 22 so that the risk of overetching the side wall spacers and hence nitride caps 20 and silicide 18 is reduced. However, such trade offs in contact opening width and the reduced risk of overetch place sever constraints on the photomask alignment processes used to define contact opening 28.
This invention arose out of the need to provide a wider contact opening without the risk of undesirably etching the semiconductor substrate and certain semiconductor device components. In the context of this document, "contact opening" is intended to include any opening in a layer, including but not limited to openings formed within insulating or other layers and within which capacitors are formed. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon) and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure including, but not limited, to the semiconductive substrates described above.